Signal Name Total Product Terms Product Terms Location Power Mode Pin Number PinType Pin Use
rom_source_is_ram 2  1_1 1_2 MC1 LOW   (b) (b)
rom_base_bank_0 2  2_1 2_2 MC2 LOW 35 I/O I
rom_bank_c000_enable<0> 2  3_1 3_2 MC3 LOW   (b) (b)
rom_bank_c000_3 2  4_1 4_2 MC4 LOW   (b) (b)
rom_bank_c000_2 2  5_1 5_2 MC5 LOW 36 I/O I
rom_bank_c000_1 2  6_1 6_2 MC6 LOW 37 I/O I
rom_bank_c000_0 2  7_1 7_2 MC7 LOW   (b) (b)
ram_bank_3 2  8_1 8_2 MC8 LOW 39 I/O I
ram_bank_2 2  9_1 9_2 MC9 LOW 40 I/O I
ram_bank_1 2  10_1 10_2 MC10 LOW   (b) (b)
ram_rom_adr<10> 3  10_3 10_4 11_1 MC11 LOW 41 I/O O
ram_ce 14  11_2 11_3 11_4 11_5 12_1 12_2 12_3 12_4 12_5 13_1 13_2 13_3 13_4 13_5 MC12 LOW 42 I/O O
ram_bank_0 2  14_3 14_4 MC13 LOW   (b) (b)
floppy_mode<3> 2  14_1 14_2 MC14 LOW 43 I/O I
d7_ram_rom 2  15_1 15_2 MC15 LOW 46 I/O I/O
floppy_mode<2> 2  16_1 16_2 MC16 LOW   (b) (b)
ram_rom_oe 1  17_1 MC17 LOW 49 I/O O
floppy_mode<1> 2  18_1 18_2 MC18 LOW   (b) (b)

Signals Used By Logic in Function Block
  1. $OpTx$FX_DC$501
  2. $OpTx$FX_DC$502
  3. $OpTx$FX_DC$556
  4. $OpTx$FX_SC$520
  5. N104/N104_D2
  6. data<3>.PIN
  7. data<2>.PIN
  8. data<1>.PIN
  9. data<0>.PIN
  10. N27/N27_D2
  11. adr<10>
  12. adr<12>
  13. adr<13>
  14. adr<14>
  15. adr<15>
  16. adr<7>
  17. data<7>.PIN
  18. floppy_mode<0>
  19. floppy_mode<1>
  20. floppy_mode<2>
  21. floppy_mode<3>
  22. floppy_mode_0__or0000/floppy_mode_0__or0000_D2
  23. phi2
  24. ram_bank_0
  25. ram_bank_1
  26. ram_bank_2
  27. ram_bank_3
  28. ram_bank_4
  29. reset
  30. rom_bank_c000_0
  31. rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2
  32. rom_bank_c000_1
  33. rom_bank_c000_2
  34. rom_bank_c000_3
  35. rom_bank_c000_enable<0>
  36. rom_base_bank_0
  37. rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2
  38. rom_source_is_ram
  39. rw