FB1
FB2
FB3
FB4
FB5
FB6
FB7
FB8
Signal Name
Total Product Terms
Product Terms
Location
Power Mode
Pin Number
PinType
Pin Use
(unused)
0
MC1
(b)
(b)
riot_ready_in_IBUF$BUF0/riot_ready_in_IBUF$BUF0_TRST
1
2_1
MC2
LOW
63
I/O
I
check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2
1
3_1
MC3
LOW
(b)
(b)
$OpTx$FX_DC$515
1
4_1
MC4
LOW
(b)
(b)
centronics_data
3
5_1
5_2
5_3
MC5
LOW
64
I/O
O
centronics_strobe
2
6_1
6_2
MC6
LOW
65
I/O
O
turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2
2
7_1
7_2
MC7
LOW
(b)
(b)
centronics_clk
3
8_1
8_2
8_3
MC8
LOW
66
I/O
O
summer
2
9_1
9_2
MC9
LOW
67
I/O
O
turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2
2
10_1
10_2
MC10
LOW
(b)
(b)
density<2>
4
11_1
11_2
11_3
11_4
MC11
LOW
68
I/O
O
density<1>
4
12_1
12_2
12_3
12_4
MC12
LOW
70
I/O
O
happy_a12__or0001/happy_a12__or0001_D2
2
13_1
13_2
MC13
LOW
(b)
(b)
density<0>
5
14_1
14_2
14_3
14_4
14_5
MC14
LOW
71
I/O
O
track_hi<6>
4
15_1
15_2
15_3
15_4
MC15
LOW
72
I/O
O
$OpTx$FX_DC$531
2
16_1
16_2
MC16
LOW
(b)
(b)
$OpTx$FX_DC$502
3
17_1
17_2
17_3
MC17
LOW
73
I/O
I
$OpTx$FX_DC$554
8
17_4
18_1
18_2
18_3
18_4
18_5
1_1
1_2
MC18
LOW
(b)
(b)
Signals Used By Logic in Function Block
$OpTx$FX_DC$461
$OpTx$FX_DC$475
$OpTx$FX_DC$492
d7_ram_rom.PIN
data<6>.PIN
data<5>.PIN
data<4>.PIN
data<2>.PIN
data<1>.PIN
data<0>.PIN
N2/N2_D2
adr<0>
adr<10>
adr<11>
adr<12>
adr<13>
adr<14>
adr<15>
adr<1>
adr<4>
adr<5>
adr<6>
adr<7>
adr<8>
adr<9>
centronics_clk
centronics_data
centronics_strobe
check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2
data<7>.PIN
density<0>
density<1>
density<2>
floppy_mode<0>
floppy_mode<1>
floppy_mode<2>
floppy_mode<3>
reset
rom_bank_c000_enable<0>
rw
track_hi<6>
turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2